1. Field of the Invention
One or more aspects of the present invention relate generally to synchronizing events across multiple execution pipelines, and more particularly to synchronizing the events using signals that may incur varying amounts of latency.
2. Description of the Related Art
Multiple execution pipelines are conventionally used to increase processing throughput. Sometimes it is necessary to synchronize the multiple pipelines in order to process data from a common starting point. Some conventional synchronization mechanisms require that each of the multiple pipelines signal their execution status to each other or a central synchronization unit in a single clock cycle. As chip die sizes increase, the distance that the signals must travel across a die may increase beyond what can be accomplished in a single clock cycle and in order to meet the chip-level timing constraints, the signals are pipelined. Pipelining the signals may result in varying latencies for each signal complicating synchronization when multiple synchronization events occur in sequence.
When the signals are pipelined, a conventional handshake synchronization mechanism is used so that each sender of a signal is acknowledged by the central synchronization unit or every other execution pipeline. Unfortunately, the round trip latency incurred for the handshaking synchronization of each synchronization event reduces the processing throughput of the multiple execution pipelines.
As the foregoing illustrates, what is needed in the art is the ability to synchronize multiple execution pipelines when multiple synchronization events may occur in sequence and the synchronization signals are pipelined to meet chip-level timing constraints.